The simulation of a master-slave event set processor

Abstract

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. This paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principle processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation pro gram modeling this sytem was constructed, and was run with trace output taken from two different simulation programs. Out put from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and in terprocessor communication times). A comparison between ac tual and simulated run times for a one-processor system was used to assist in the validation of the simulation.