Multiprocessor features of the HP Corporate Business Servers
- 31 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors describe the multiprocessor features of Hewlett-Packard's (HP's) new high-performance Corporate Business Servers. The present implementation uses 60-MHz PA-RISC (reduced instruction set computer) CPUs interconnected with a high-speed processor memory bus to support symmetric eight-way multiprocessing. The focus is on the features and design decisions which allow the system to achieve excellent online transaction processing performance and efficient multiprocessor scaling. The system was designed to provide for scalability of processors, memory, and I/O adapters, and to accommodate multiple generations of processors. The system makes use of fast CPUs with large caches, a high-speed pipelined processor memory bus, duplicate cache tags on the processor modules for fast coherency checking, cache-to-cache transfers for coherency resolution, and highly interleaved large physical memory.<>Keywords
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