A Pipelined 330-MHz Multiplier
- 1 June 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (3), 411-416
- https://doi.org/10.1109/jssc.1986.1052543
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- A Fine-Line nMOS IC for Raster-Scan Control of a 500-MHz Electron-Beam Deflection SystemIEEE Journal of Solid-State Circuits, 1982
- Completely iterative, pipelined multiplier array suitable for VLSIIEE Proceedings G (Electronic Circuits and Systems), 1982
- Why systolic architectures?Computer, 1982
- Effective Pipelining of Digital SystemsIEEE Transactions on Computers, 1978
- Special-purpose hardware for digital filteringProceedings of the IEEE, 1975
- Pipeline Iterative Arithmetic ArraysIEEE Transactions on Computers, 1975