Laying the Power and Ground Wires on a VLSI Chip

Abstract

This paper presents the approach of MIT's Placement-Interconnect (PI) Project to routing noncrossing VDD and GND trees in single-layer metal. The input to the power-ground phase is a set of rectangular modules on a rectangular chip. There is one VDD pad, one GND pad and each module has one VDD terminal, one GND terminal, and a current requirement. The power-ground phase calculates a cycle that passes through every module once, dividing the VDD terminals from the GND terminals. This splits the chip into a VDD region and a GND region. Signal-routing techniques find a short Steiner tree in the VDD region that connects the VDD terminals to the VDD pad. This Steiner tree consists of minimum width metal wires. The same techniques route the GND tree. Using each module's current requirement, tree-traveral determines the current requirement and required width of each wire of the trees. Techniques used to widen overcrowded channels widen the wires, producing the final VDD and GND trees.