Vanadium ion (V+) implantation has been successfully applied to the formation of semiinsulating 6H‐SiC layers. The resistivity of V+‐implanted layers strongly depended on the conduction type of initial 6H‐SiC crystals. The resistivity at room temperature exceeded 1012 Ω cm and 106 Ω cm for p‐ and n‐type samples, respectively. Compensation mechanism is discussed based on the temperature dependence of resistivity. This technique will be useful for device isolation, edge termination, and reduction of parasitic impedance of SiC devices.