Double sampling in switched-capacitor delta-sigma A/D converters

Abstract

The achievable signal-to-noise ratio is switched-capacitor delta-sigma modulation analog-to-digital converters is set by the oversampling clock frequency divided by twice the signal bandwidth. The use of double sampling in the switched-capacitor integrators to achieve a factor of two increase in the oversampling factor without reducing the settling time of the operational amplifier is proposed. Detailed simulations have shown that for sufficiently small capacitor mismatch, the double-sampling schemes provide a significant increase in SNR. The larger the desired SNR, the more sensitive the circuit is to capacitor mismatch. It is concluded that the random gain implementation is preferred over the alternating gain scheme, because the former spectrally spreads the effect of the capacitor mismatch.