Pipelined VLSI/WSI architectures supporting image coding transforms are defined and evaluated in the paper. The structures proposed in the paper have been derived by considering a common algorithmic kernel of the set of examined transforms. The possibility of reducing the computations to a common algorithmic version allows definition of flexible structures characterized by a “basic” pipeline - performing the common kernel of computation - and by transform-dependent input and output stages. Three different pipelines have been defined and figures of merit, such as silicon area occupation and throughput, have been evaluated for architectures comparisons.