VLSI Architectures For Block Matching Algorithms

Abstract

This paper discusses architectures for realization of block matching algorithms with emphasis on highly concurrent systolic array processors. A three step mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of 2-dimensional and 1-dimensional systolic arrays are presented. The needed array size, the transistor count and the maximum frame rate for processing video telephone and TV signals have been estimated.© (1988) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.