NAPA C: compiling for a hybrid RISC/FPGA architecture
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- A high-performance microarchitecture with hardware-programmable functional unitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Garp: a MIPS processor with a reconfigurable coprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Baring it all to software: Raw machinesComputer, 1997
- Constructing hardware-software systems from a single descriptionJournal of Signal Processing Systems, 1996
- Software pipelining: an effective scheduling technique for VLIW machinesPublished by Association for Computing Machinery (ACM) ,1988