A 3-D sidewall flash EPROM cell and memory array
- 1 August 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 14 (8), 415-417
- https://doi.org/10.1109/55.225597
Abstract
A new 3-D sidewall flash EPROM cell has been implemented in a novel memory array. The sidewall cell is a single-transistor stacked gate cell built on the sidewalls of a silicon pillar. The gates surround the pillar and current flows vertically from top to bottom of the pillar. The cell size approaches the square of the minimum pitch and is less than 40% of that of the conventional NOR-type structure. The cell and array architecture promise to be highly scalable.Keywords
This publication has 2 references indexed in Scilit:
- A 5 V-only virtual ground flash cell with an auxiliary gate for high density and high speed applicationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A novel memory cell using flash array contactless EPROM (FACE) technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002