Comparative studies on the stability of polymer versus SiO2 gate dielectrics for pentacene thin-film transistors

Abstract

The authors report on the electrical reliabilities of poly-4-vinyl phenol (PVP) and $\mathrm{Si}{\mathrm{O}}_2$ gate dielectrics for pentacene thin-film transistors (TFTs). $\mathrm{Si}{\mathrm{O}}_2$ films were grown by dry oxidation and PVP films were prepared by spin coating and subsequent cross-linking at $175°\mathrm{C}$ for $15\min$ . The pentacene TFTs with the PVP cured for $15\min$ exhibited a large hysteresis and an abnormal drain-current increase under a gate bias stress over time, while the other TFT with $\mathrm{Si}{\mathrm{O}}_2$ displayed a small hysteresis but its drain current decreases with time. The hysteresis behaviors induced by PVP and $\mathrm{Si}{\mathrm{O}}_2$ were opposite to each other in the gate bias swing direction, due to the difference in hysteresis mechanism between the two types of TFTs. Comparing their hysteresis behavior, the authors fabricated a far more reliable pentacene TFT with PVP by extending the PVP curing time to $1\mathrm{h}$ . Our improved device with PVP exhibited no hysteresis and persistent toughness to the gate bias stress.