CMOS layout design of the hysteresis McCulloch–Pitts neuron

Abstract

A McCulloch–Pitts neuron is the simplified neuron model which has been successfully used for many optimisation problems. The neural network with the hysteresis property can suppress the oscillatory behaviours of neural dynamics so that the convergence time is shortened. In this paper, digital CMOS layout design of the hysteresis McCulloch–Pitts neuron is presented. Based on simulation results using the hysteresis McCulloch–Pitts binary neuron model, a 6-bit fixed point 2's complement arithmetic was adopted for the calculation of the input U of each neuron. Each neuron needs 204 transistors and requires a 399λ × 368λ layout area using the MOSIS scalable CMOS/bulk (SCMOS) VLSI technology with 2 μm rule of P well, double level metal. Layout design of the hysteresis McCulloch—Pitts neuron chip was completed, and fabrication of the chip and the design for the test circuit for the fabricated CMOS VLSI chip are underway at present.