An automated process for compiling dataflow graphs into reconfigurable hardware
- 1 February 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 9 (1), 130-139
- https://doi.org/10.1109/92.920828
Abstract
We describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into dataflow graphs and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces dataflow graphs and a dataflow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application programmer.Keywords
This publication has 9 references indexed in Scilit:
- PipeRench: a coprocessor for streaming multimedia accelerationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Text searching on Splash 2Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Searching genetic databases on Splash 2Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Convolution on Splash 2Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Reconfigurable Architectures for System Level Applications of Adaptive ComputingVLSI Design, 2000
- Seeking solutions in configurable computingComputer, 1997
- Baring it all to software: Raw machinesComputer, 1997
- The Khoros software development environment for image and signal processingIEEE Transactions on Image Processing, 1994
- Image processing on a custom computing platformLecture Notes in Computer Science, 1994