Comparing two-level and ordered binary decision diagram representations of logic functions
- 1 May 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 12 (5), 722-723
- https://doi.org/10.1109/43.277617
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplicationIEEE Transactions on Computers, 1991
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- Lower bounds for VLSIPublished by Association for Computing Machinery (ACM) ,1981