Optimizing N-p-n and P-n-p heterojunction bipolar transistors for speed

Abstract

The comparative optimization of N-p-n and P-n-p Al-GaAs/GaAs heterojunction bipolar transistors for high speed in both microwave and switching applications is studied. The analysis uses a compact transistor model and considers devices with self-aligned geometries, passivated extrinsic junctions, and graded base regions, as well as more conventional structures. We find that in all cases, P-n-p structures are capable of operation at speeds approaching those of N-p-n structures, provided the device designer uses the unique advantages of each to optimize them differently. Both devices require sacrificing some of the speed potential of the low-resistance electron path in order to improve the performance of the high-resistance hole path.