On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices
- 2 March 2004
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- An interconnect-aware methodology for analog and mixed signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approachPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On-chip wiring design challenges for gigahertz operationProceedings of the IEEE, 2001
- Figures of merit to characterize the importance of on-chip inductanceIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1999
- A Top-Down, Constraint-Driven Design Methodology for Analog Integrated CircuitsPublished by Springer Nature ,1997