Influence of buffer layer thickness on memory effects of SrBi2Ta2O9∕SiN∕Si structures

Abstract

We deposited ${\mathrm{SrBi}}_2{\mathrm{Ta}}_2{\mathrm{O}}_9$ (SBT) thin films on silicon–nitride $\left(\mathrm{SiN}\right)$ buffered $\mathrm{Si}\left(100\right)$ substrates to form metal–ferroelectric–insulator–semiconductor structures and observed a significant influence of the buffer layer thickness on the magnitude and direction of the capacitance–voltage ($C–V$ ) memory window. As the $\mathrm{SiN}$ buffer layer thickness was decreased from $6\mathrm{nm}$ to $2\mathrm{nm}$ , the $C–V$ memory hysteresis direction changed from memory direction dominated by ferroelectric polarization (i.e., counterclockwise for $n\text{-}\mathrm{Si}$ ) to a trapping-related hysteresis direction (i.e., clockwise for $n\text{-}\mathrm{Si}$ ). The memory windows for both cases exhibited a similar temperature dependence. The memory window approached zero at temperatures from $340°\mathrm{C}$ to $380°\mathrm{C}$ , which corresponds to the Curie temperature $\left(T_C\right)$ of the ferroelectric SBT films. When the temperature was returned to room temperature, the hysteresis windows were recovered. A detailed study has led us to believe that the switching of polarization of the ferroelectric SBT plays a key role in the observed temperature dependence, for both the ferroelectric polarization-dominated and the trapping-dominated memory window.