PLEST: A Program for Area Estimation of VLSI Integrated Circuits
- 1 January 1986
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- CHAMP: Chip Floor Plan for Hierarchical VLSI Layout DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- The Effect of Register-Transfer Design Tradeoffs on Chip Area and PerformancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983