As linewidths decrease and the number of layers of interconnection increases, the problems of topographically uneven surfaces in VLSI processing become more severe. Several methods to smooth the topography, i.e., “planarize” it, have been suggested. Some of these use a coating spun‐on in the manner used to apply photoresists (1–4). The effectiveness of this process and a subsequent “reflow” bake have been investigated using several different resists with isolated or coarse line structures (5, 6). Preliminary reports on the effect of circuit structure density have been reported by us (7) and, more recently, by others (8). In this paper, our results using scanning electron micrographs (SEM), interference micrographs (IM), and profilometer traces (PT) on high density, fine lines are reported. A simple, space filling model to describe the effects is presented and the implications for VLSI planarization are noted.