TdI18: Process integration of the ferroelectric memory FETs (FEMFETs) for ndro ferram

Abstract

Experimental results derived from early lots made with modified EEPROM masks are described. MIS structures formed with ferroelectric (FE) films grown on lightly doped silicon substrates have yielded FE switching properties demonstrated by hysteresis in capacitance vs voltage (CV) characteristics as the first step required to show suitability for use in high performance FEMFETs. In particular, switching attributable to polarization charge reversal inside the FE layer is observed, as opposed to tunnel injection of carriers from the silicon into the gate dielectric. Barium magnesium fluoride (BMF) and bismuth titanate FE films are currently under evaluation. Recent FEMFETs have achieved a 9.5V memory window using 20V programming, with I_on/I_off > 10⁵ for W/L = 12μm/3μm, after complete fabrication ∼ including Scratch-Protection. Some data loss is apparently associated with the BMF films having their primary P. vector nearly in the plane of the film and only a small component of P, experiencing reversal during memory hysteresis programming, as well as the reversable polarization lacking a definite coercive field.