Design and Verification of Large-Scale Computers by Using DDL
- 1 January 1979
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 360-366
- https://doi.org/10.1109/dac.1979.1600137
Abstract
This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.Keywords
This publication has 2 references indexed in Scilit:
- Translation of a DDL Digital System Specification to Boolean EquationsIEEE Transactions on Computers, 1969
- A Digital System Design Language (DDL)IEEE Transactions on Computers, 1968