Logic Partitioning for Minimizing Gate Arrays
- 1 April 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 2 (2), 117-121
- https://doi.org/10.1109/tcad.1983.1270028
Abstract
This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.Keywords
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