1-µm MOS process using anisotropic dry etching

Abstract

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.