A 1.5 V single-supply one-transistor CMOS EEPROM
- 1 June 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 16 (3), 195-200
- https://doi.org/10.1109/JSSC.1981.1051573
Abstract
Describes a 1.5 V single-supply one-transistor p-channel CMOS EEPROM array which is fabricated with a double polysilicon gate 7-mask CMOS technology. Avalanche injection and Fowler-Nordheim emission are used as very low power programming mechanisms. A thin oxide of 28 nm allows write and erase voltages below -30 V. They are generated on-chip by voltage multipliers and fed by 1.5 V logic circuitry to the matrix array. Results measured on a 16/spl times/4 bit word-erasable test array are presented.Keywords
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