1-M sample/sec 12-bit low-power pipelined A/D converter
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1360-1363
- https://doi.org/10.1109/iscas.1990.112384
Abstract
A 12-b switched-capacitor (SC) pipelined A/D converter has been developed in the framework of the CERN LAA project for particle physics detector R&D. The integral linearity of the converter is improved by an autocalibration cycle compensating the ratio error between two nominally identical capacitors. The circuit has been manufactured using a low-voltage 3- mu m CMOS technology. The active chip area including registers and clocking circuitry is 5.25 mm/sup 2/. Experimental results indicate 11-b resolution for 1-MHz sampling frequency, with only 6-mW power consumption.Keywords
This publication has 3 references indexed in Scilit:
- 8-bit micropower algorithmic A/D convertorElectronics Letters, 1987
- New clock feedthrough cancellation technique for analogue MOS switched-capacitor circuitsElectronics Letters, 1982
- Class AB CMOS amplifier micropower SC filtersElectronics Letters, 1981