Barrier layers for realization of high capacitance density in SrTiO3 thin-film capacitor on silicon

Abstract

High dielectric constant SrTiO₃ thin films were sputter deposited on barrier layers/Si substrate to fabricate a capacitor for dynamic random access memories. Dielectric constant (ε_r) values of 140–210 were achieved for the 150‐nm‐thick SrTiO₃ films using a Pt/Ti or Pt/Ta double‐layer barrier. In the Pt(50 nm)/Ti(10 nm), Pt(50 nm)/Ti(50 nm), and Pt(50 nm)/Ta(10 nm) barrier, effective ε_r decreased by annealing in the temperature range between 450 and 550 °C, where the interdiffusion of Pt and Si was confirmed by x‐ray diffraction analysis and cross‐sectional transmission electron microscopy. In the Pt(50 nm)/Ta barrier, increase of the Ta thickness from 10 to 50 nm brought out a remarkable improvement of endurance to high‐temperature annealing. That is, in the Pt(50 nm)/Ta(50 nm) barrier, large ε_r value (∼200) was maintained even with annealing at up to 700 °C.