Peripheral circuits for one-transistor cell MOS RAM's
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (5), 255-261
- https://doi.org/10.1109/jssc.1975.1050608
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- An 8K B random-access memory chip using the one-device FET cellIEEE Journal of Solid-State Circuits, 1973
- Storage array and sense/refresh circuit for single-transistor memory cellsIEEE Journal of Solid-State Circuits, 1972