Investigation of Radiation Effects and Hardening Procedures for CMOS/SOS

Abstract

Ionizing radiation effects and hardening procedures have been investigated using simple CMOS/SOS circuits fabricated with SiO2 gate insulators. A modified gate oxidation process using steam and HCl has resulted in improved gate oxide hardness -- with threshold voltage shifts of less than two volts up to a total dose of 106 rads(Si). Radiation-induced n-channel leakage currents were reduced by more than two orders of magnitude by using a deep boron ion implant and appropriate process ing techniques. Post-irradiation values of less than 0.5μA/mil have been obtained using this procedure. Studies of charge buildup at the silicon-sapphire interface indicate an effective positive charge in the range of 1011 cm-2 to 1012 cm-2 - peaking at a total dose of about 105 rads (Si). This effective charge decreases for increasing doses above 5×105 rads(Si). The decrease is attributed to radiation-induced interface states.