Capacitance-Voltage Characteristics of Metal Barriers on p PbTe and p InAs: Effects of the Inversion Layer

Abstract

The dependence of the capacitance C on the voltage is derived for metal‐semiconductor barriers in which there is a strong inversion layer at the metal‐semiconductor interface, a case of interest in the study of surface effects and in applications for laser structures. Experimental results for evaporated lead and tin barriers on p PbTe at 77 °K and for evaporated gold barriers on p InAs at 77 and 4.2 °K are presented and compared to calculations performed with the inversion layer model. Both the theory and experiment show an essentially linear dependence of C⁻² with voltage, as in the usual Schottky barrier, but a voltage intercept which is surprisingly dependent on band‐structure parameters, bulk carrier concentration, and temperature. Reasonable quantitative agreement between the theory and experiment is obtained. In all cases the presence of a strong inversion layer can be clearly established. The analysis of the capacitance‐voltage data, however, gives only a lower limit to the amount of inversion present.