Techniques have been developed for the interconnection of a large number of gates on an integrated-circuit wafer to achieve multiple-bit logic functions on a single slice of silicon. An analysis of popular logic types indicates that the transistor-transistor-logic (TTL) circuit is well suited for use in such arrays. The output of two representative production lines has been shown to provide an economic yield for arrays of 10 to 30 gates on each chip. Experimental results are presented for logic-array designs involving the interconnection of 47 and 108 gates on the wafer. Packaging, rather than yield, appears to be the remaining challenge in the develepment of the concept. Ultimately, the achievement of a significant portion of a computer arithmetic function on a single wafer appears entirely feasible.