Hierarchical Circuit Extraction with Detailed Parasitic Capacitance

Abstract

This paper describes a hierarchical MOS layout verification program called IV. IV extracts a circuit netlist from a MOS layout and then compares this netlist to a reference circuit netlist obtained from a schematic. The circuit extraction phase of IV is described in detail. A unique characteristic of the program is the treatment of parasitic capacitance. IV is currently being used in a production environment to extract circuits in a variety of NMOS and CMOS processes.