An SIMD array processor augmented with bypass connections, called mesh with bypass connections (MBC), is presented. This architecture reduces the diameter of the n*n array from O(n) to O(1). MBC significantly improves the performance of the array processor, especially in global operations; finding a minimum/maximum, average and sum take O(log/sub 2/n) time, which require O(n) with ordinary mesh connections, O(n/sup 1/3/) in mesh with multiple broadcast. Matrix multiplication can be done in O(n) time. Image processing operations such as histogramming, median row finding, convolution and image projection can be efficiently mapped onto the architecture. MBC using circuit switching instead of store-and-forward outperforms the mesh, mesh with broadcast and mesh with multiple broadcast. Hardware augmentations for bypass on the ordinary mesh do not hurt the homogeneity of the processor; thus MBC can be implemented with VLSI technology to get a massive parallelism.<>