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SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture
Home
Publications
SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture
SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture
KM
K. Murakami
K. Murakami
NI
N. Irie
N. Irie
MK
M. Kuga
M. Kuga
ST
S. Tomita
S. Tomita
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24 August 2005
proceedings article
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/isca.1989.714527
Abstract
No abstract available
Cited by 17 articles