A VLSI implementation of residue adders
- 1 March 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 34 (3), 284-288
- https://doi.org/10.1109/tcs.1987.1086130
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- An area-time efficient NMOS adderIntegration, 1983
- Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field ArithmeticIEEE Transactions on Computers, 1983
- Models for VLSI implementation of residue number system arithmetic modulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- The Design of Error Checkers for Self-Checking Residue Number ArithmeticIEEE Transactions on Computers, 1983
- Implementation of a fast digital processor using the residue number systemIEEE Transactions on Circuits and Systems, 1981
- Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic TransformsIEEE Transactions on Computers, 1980
- A highly efficient residue-combinatorial architecture for digital filtersProceedings of the IEEE, 1978
- Residue Number Scaling and Other Operations Using ROM ArraysIEEE Transactions on Computers, 1978
- Multipliers for residue-number-arithmetic digital filtersElectronics Letters, 1977
- A Novel Implementation Method for Addition and Subtraction in Residue Number SystemsIEEE Transactions on Computers, 1974