AES as stream cipher on a small FPGA
- 22 September 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 3329, 4
- https://doi.org/10.1109/iscas.2006.1692639
Abstract
This paper presents a very low area design for the advanced encryption standard (AES) capable of functioning in three of its feedback modes to provide flexible support for its use as a stream cipher. The architecture is based around an 8-bit application specific instruction processor (ASIP) and includes UARTs to support asynchronous serial I/O. The entire design fits within the smallest Xilinx Spartan-II FPGA (XC2S15), occupying 174 slices and two block memories. The design achieves a throughput of 2.3 Mbps with a 70MHz clock in OFB, CTR and CFB modes. The size is approximately 27% smaller than a comparable RC4 designKeywords
This publication has 3 references indexed in Scilit:
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