Representation of control and timing behavior with applications to interface synthesis
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- Sehwa: a software package for synthesis of pipelines from behavioral specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MAHA: A Program for Datapath SynthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A General Methodology for Synthesis and Verification of Register-Transfer DesignsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984