A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features

Abstract

Reports on a new 200 ns highly reliable, 16384 bit (2K/spl times/8), thin oxide floating gate electrically erasable and programmable read-only memory-e/SUP 2/PROM. The part can be written and erased by tunneling of electrons to and from the floating gate within 10 ms by applying a DC signal of 21 V to V/SUB pp/ . Improved yield and performance through minimizing the thin oxide area is achieved by incorporating a single direct wafer stepper masking step to define a minimum (1.5 /spl mu/m diameter) thin oxide injecting area. A new array architecture has made it feasible to selectively erase or write a single byte. Improved reliability is achieved by incorporating an on-chip V/SUB pp/ pulse shape generator which minimizes thin oxide stress. Endurance related testing features designed into the part allow efficient endurance screening of potentially `weak' parts.