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Interconnects for a Multi-Layer Three-Dimensional Silicon Architecture
Home
Publications
Interconnects for a Multi-Layer Three-Dimensional Silicon Architecture
Interconnects for a Multi-Layer Three-Dimensional Silicon Architecture
KH
Katherine J. Herrick
Katherine J. Herrick
RK
Robert T. Kihm
Robert T. Kihm
LK
Linda P. B. Katehi
Linda P. B. Katehi
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1 October 2000
conference paper
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/euma.2000.338761
Abstract
No abstract available
Keywords
PATCH ANTENNA
FLIP CHIP
SILICON
THREE DIMENSIONAL
Cited by 3 articles