A system has been constructed and used for on-line acquisition of data at the Iowa State Synchrotron Laboratory. The principal components include eight Victoreen analog to digital converters (ADC) and a fast general purpose digital computer (SDS 910) along with the necessary interface circuitry to couple to the digitized outputs of scalers, clocks, etc. Although quite flexible in application, the ADC-to-computer interface was designed especially for efficient use (minimum deadtime and bias) both with an accelerator having a beam burst of about 100 microseconds duration and for continuous operation. To minimize ADC deadtime ineither circumstance, each 8Mc/sec ADC, equipped with an analog buffer, is connected through a plugboard to a digital buffer register synchronized to the ADC. This permits readout of the digitized pulse heights in less than one microsecond. In experiments where the ADC's operate completely independently of one another, a hardware option is provided to interpret the buffer register contents as addresses in the computer memory. This option eliminates the necessity for software programming of data input: the contents of the associated word in memory may be either incremented or decremented automatically in a minimum of two computer cycles. Some biasing in efficiency normally occurs in multiple ADC systems at high counting rates when two or more registers are waiting for readout. To reduce such bias to a negligible amount, logic governing data transfer to the computer sequences through a hierarchy of register preferences with a periodicity of 128 microseconds.