CMOS scaling is requiring increased attention on several aspects of ultrathin oxides, including both physical and electrical properties. In particular, surface preparation and interface quality will play an increasingly important role as the gate oxide thickness is scaled down to below 30 angstroms for sub-0.1 micrometer devices. This means that standard thermal desorption of sacrificial oxides or even H-terminated surfaces will have to be closely investigated to determine if the requirements for interface roughness and uniformity can still be met, or whether new preparation techniques will have to be used. Growth of oxides in the ultrathin regime is also a concern because of uniformity and reproducibility problems using furnaces, including pinhole formation in films. Physical and electrical characterization of ultrathin oxides presents difficulties with most currently used techniques. Measurement of the oxide thickness below 30 angstrom involves substantial uncertainties in standard techniques such as spectroscopic ellipsometry form impurities and interface roughness and in C- V analysis from large tunneling currents and poly-depletion effects. One possibility for overcoming these problems is to use the direct tunneling current to determine the electrical thickness of the oxides. It is important to characterize the effect of decreasing oxide thickness in the ultrathin regime on fundamental parameters such as the electron effective mass m* and the band gap, especially for predicting the electrical behavior of these oxides. Boron penetration effects also present problems for device operation with the ultrathin oxides which need to be addressed. The combination of these concerns leads toward alternate gate dielectric materials with higher dielectric constants and higher resistance to B diffusion.