A new analytic model for amorphous silicon thin-film transistors

Abstract

We present a new theory describing current‐voltage characteristics of amorphous silicon thin‐film transistors. We calculate the output conductance in saturation by considering channel shortening effects caused by the space‐charge‐limited current in the pinch‐off region. In this model the drain current is expressed through the free‐carrier concentration at the source side of the channel. This allows us to obtain an accurate description of the different operating regimes of a thin‐film transistor using one equation that accounts for the dependence of the free‐carrier concentration in the channel for different regimes. Our model is in good agreement both with experimental data and the results of our two‐dimensional computer simulation. This approach allows one to account for different distributions of localized states in the energy gap. The model has also been developed to be incorporated into a circuit simulator and used for computer‐aided design of amorphous silicon integrated circuits.