Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance
- 22 July 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 24 (6), 411-413
- https://doi.org/10.1109/led.2003.813363
Abstract
For the first time, mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain workfunction and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial performance advantage versus doped source/drain is demonstrated.Keywords
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