Nanowire-based multiple quantum dot memory
- 16 October 2006
- journal article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 89 (16)
- https://doi.org/10.1063/1.2362594
Abstract
The authors propose and demonstrate an alternative memory concept in which a storage island is connected to a nanowire containing a stack of nine InAs quantum dots, each separated by thin InP tunnel barriers. Transport through the quantum dot structure is suppressed for a particular biasing window due to misalignment of the energy levels. This leads to hysteresis in the charging/discharging of the storage island. The memory operates for temperatures up to around 150K and has write times down to at least 15ns. A comparison is made to a nanowire memory based on a single, thick InP barrier.Keywords
This publication has 11 references indexed in Scilit:
- InAs1-xPx Nanowires for Device EngineeringNano Letters, 2006
- Low-cost and nanoscale non-volatile memory concept for future silicon chipsNature Materials, 2005
- Nanowire Single-Electron MemoryNano Letters, 2005
- Electron transport in InAs nanowires and heterostructure nanowire devicesSolid State Communications, 2004
- Few-Electron Quantum Dots in NanowiresNano Letters, 2004
- One-dimensional heterostructures in semiconductor nanowhiskersApplied Physics Letters, 2002
- Silicon-based single-electron memory using a multiple-tunnel junction fabricated by electron-beam direct writingApplied Physics Letters, 1999
- Progress and outlook for MRAM technologyIEEE Transactions on Magnetics, 1999
- Silicon single electron memory cellApplied Physics Letters, 1998
- Measurement of single electron lifetimes in a multijunction trapPhysical Review Letters, 1994