E‐beam direct slice writing has been utilized to fabricate a 55% linear shrink of the SBP9989, a 16‐bit I 2L microprocessor in the familiar TI SBP9900 series. The scaled device contains approximately 5 K gates and the chip area is 14.4 mm2 as compared with 37.1 mm2 for the full‐sized chip. The chip layout is maintained in a database which can be easily manipulated to change design rules, scale selected geometries (p n p base width, collector size, etc.) or vary the overall scaling factor. The design requires minimum geometries of 1.25 μm and an overall process registration of ±0.75 μm. Patterns were delineated in TI‐323A positive and TI‐309 negative electron resists using EBMIII, a vector‐scanned, laser‐controlled electron beam exposure machine with a minimum beam diameter of 0.4 μm and level‐to‐level registration accuracy of <±0.25 μm. The oxide‐separated, double‐level‐metal fabrication process used ion implantation and anisotropic plasma etching to achieve maximum control of junction depths and etch profiles, respectively. Fabricated units were fully functional from −55 °C to +125 °C and showed a speed improvement of 2× at one‐half the power of the full‐size chip.