Hot-electron design considerations for high-density RAM chips

Abstract

This paper presents a channel hot-electron degradation model that is valid for both fixed and time-varying bias conditions. A simple relationship has been derived for the practical case of identical, repetitive pulses. The model uses gate current measurements of the emitted hot electrons to functionally relate FET structural parameters and bias conditions to the resulting threshold shift over time. Incorporated into circuit simulation programs, it has been used to predict long-term circuit behavior. Modeling results are given for the memory cell, word decoder, set latch driver, and sense amplifier drawn from a theoretical study of a 256-kbit dynamic RAM chip.