Analysis and design of a transistor linear-delay circuit

Abstract

In this paper an analysis is presented of the emitter-coupled linear-time-delay circuit as well as a systematic design procedure which starts with a practical set of specifications. Some important fundamental limitations on the operation and design of the circuit are also presented. Experimental data are included to give an idea of the range of validity of the theory. A range of the ratio of maximum-to-minimum pulse width as high as several hundred has been obtained as compared with 10 or 20 obtainable from a similar vacuum-tube circuit. A ratio in excess of 30 was obtained with a deviation from linearity of less than 3%. Stages of this circuit have been successfully operated in cascade.