In building a proof of concept model of a systolic processor, several design issues are resolved. Flexibility is achieved through a hierarchy of software which resides on a host computer and through extensive interface and control hardware. Buffer memories with pro-grammable address generators are provided in the interface. The control system is general enough to support command chaining and loops. Each cell of the systolic array is equipped with its own memory which allows a single cell design to perform a number of algorithms. As a result of designing for flexibility, the system can accommodate a wide variety of algorithms, data representations, and problem dimensions. A useful system computation rate of 200 million operations per second (MOPS) is achieved with a peak rate of 350 MOPS.