With the trend toward higher circuit density and finer lines, printed circuit inspection becomes more important both in terms of assuring adequate functional capability, as well as long term reliability. Visual inspection of such circuits in a high volume production environment becomes more difficult, prone to error, and expensive. Automatic optical inspection appears to provide the only effective means of performing this operation. Such a method has application not only for final product inspection, but also for inspection at intermediate stages of production including art work inspection. A practical system must be able to convert the printed circuit pattern into a binary two-dimensional representation and then to process this representation to detect flaws. Development of the binary representation is hindered by the low optical contrast presented by many printed circuit material systems. The detection of flaws depends on selecting error criteria that are indicative of circuit quality, and that are practical to implement. This paper describes a prototype automatic inspection system which uses minimum line width and line clearance criteria. This system provides high resolution and uses linear solid state arrays for sensors. The conversion to a binary representation is made after correcting for system spatial nonuniformities in the illumination, optics, and sensing elements. Internal registers, which are continually being updated, are used to store successive scans of the image. At the same time, the contents of the registers are processed in parallel using combinatorial logic to implement the error criteria.