Submicron CMOS technologies have been developed for an experimental four mega bit dynamic RAM (Random Access Memory). The main features are a trench capacitor cell, a triple-poly single-metal process, and a twin tub CMOS technology. The trench capacitor cells are formed in an optimized p-well in order to prevent leakage current between adjacent trench capacitors and to reduce soft error rate. The minimum gate lengths of NMOS and PMOS transistor are 0.8 um and 1.2 um, respectively. The technologies have been verified using test vehicles and 256k bit dynamic RAM chip.