Optimum State Assignment for Synchronous Sequential Circuits

Abstract

The problem of encoding the internal states of synchronous sequential switching circuits so as to minimize the combinational network cost is treated. Cost is defined as the number of AND-OR inputs required in the two-level implementation of each memory element input equation separately ( i.e., the cost is not reduced initially by the existence of common terms between equations). An algorithm has been developed that considers implicitly all distinct state-assignment schemes for a given state table, thus ensuring that the state assignment that results in the least "cost" combinational network is selected. Since any optimum state-assignment scheme is dependent on the type of memory element, the algorithm is designed for use with J-K flip-flop memory elements because of their wide use and versatility.